# Publications

# Conference

[5] Xiaolong Liu, Zhiqiang Huang, Jun Yin, Howard C Luong, “Magnetic-Tuning Millimeter-Wave CMOS Oscillators,” IEEE Custom Integrated Circuits Conference (CICC), April 2019

[4] Zhiqiang Huang , Howard C. Luong, “An 82-to-108GHz -181dB-FOMT ADPLL Employing a DCO with Split-Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta-Sigma TDC,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2018

[3] Zhiqiang Huang , Bingwei Jiang, Lianming Li, Howard C. Luong, “A 4.2μs-Settling-Time 3rd-Order 2.1GHz Phase-Noise-Rejection PLL Using a Cascaded Time-Amplified Clock-Skew Sub-Sampling DLL,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016

[2] Zhiqiang Huang , Howard C. Luong, “A Dithering-Less 54.79-to-63.16GHz DCO with 4-Hz Frequency Resolution Using An Exponentially-Scaling C-2C Switched-Capacitor Ladder,” IEEE Symposium on VLSI Circuits (VLSI), June 2015

[1] Zhiqiang Huang , Howard C. Luong, Baoyong Chi, Zhihua Wang and Haikun Jia, “A 70.5-to-85.5GHz 65nm Phase-Locked Loop with Passive Scaling of Loop Filter,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015

# Journal

[3]Zhiqiang Huang , Howard C. Luong, “An 82–107.6-GHz Integer-N ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta–Sigma TDC,” IEEE J. Solid-State Circuits, vol. 54, no.2, pp.358-367, Feb. 2019.

[2]Zhiqiang Huang , Bingwei Jiang, Howard C. Luong, “A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector,” IEEE Trans. on Circuits Syst. I Reg. Papers (TCASI), vol. 65, no.7, pp.2118 - 2126, July 2018.

[1]Zhiqiang Huang , Howard C. Luong, “Design and Analysis of Millimeter-Wave Digitally Controlled Oscillators With C-2C Exponentially Scaling Switched-Capacitor Ladder,” IEEE Trans. on Circuits Syst. I Reg. Papers (TCASI), vol. 64, no.6, pp.1299–1307, June 2017.